datasheet t1/e1 clock multiplier ics548-05 idt? t1/e1 clock multiplier 1 ics548-05 rev d 091511 description the ics548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from t1 and e1 frequencies. using idt?s patented analog/digital phase- locked loop (pll) techniques, the device uses a crystal or clock input to synthesize popular communications frequencies. power down modes allow the chip to turn off completely, or the pll and clock output to be turned off separately. idt manuafactures the largest variety of communications clock synthesizers for all applications. consult idt to eliminate vcxo?s, crystals, and oscillators from your board. features ? packaged in 16-pin tssop ? available in pb (lead) free package ? ideal for teleco m/datacom chips ? replaces oscillators ? 3.3 v or 5 v operation ? uses a crystal or clock input ? produces 24.704, 37.056, 32.768, or 49.152 mhz ? includes power-down features ? advanced, low-power, sub-micron cmos process ? see also the mk2049-34 for generating ? industrial temperature range available block diagram x1/iclk x2 input buffer/ crystal oscillator 1.544 mhz or 2.048 mhz clock or crystal input optional crystal capacitors clk refout msel x16 or x24 pll/clock synthesis circuitry refen pdclk
ics548-05 t1/e1 clock multiplier clock synthesizer idt? t1/e1 clock multiplier 2 ics548-05 rev d 091511 pin assignment output clock selection table power down clock selection table key: 0 = connect directly to gnd; 1 = connect directly to vdd pin descriptions key: xi, xo = crystal connections; the in put pin msel must be tied directly to vdd or gnd. for a clock input, connect the input x1 and leave x2 unconnected (floating). 12 1 11 2 10 x1/iclk x2 3 9 vdd 4 vdd dc 5 refen 6 refout 7 gnd 8 gnd msel gnd pdclk gnd dc vdd clk 16 15 14 13 16-pin tssop msel input (mhz) clk (mhz) pin 13 pins 1, (16) pin 9 0 1.544 24.704 1 1.544 37.056 0 2.048 32.768 1 2.048 49.152 refen pdclk power down selection mode pin 4 pin 11 0 0 the entire chip is off. 0 1 pll and clock output run, refout low. 1 0 refout running, pll off, clk low. 1 1 all running. pin number pin name pin type pin description 1 x1/iclk xi crystal connection. connect this pin to a crystal or clock input. 2, 3, 8 vdd power connect to +3.3 v or +5 v. all vdd?s must be the same. 4 refen input reference clock enable. see table above. connect to gnd for best jitter/phase noise. 5, 6, 7, 12 gnd power connect to ground. 9 clk output clock output set by input status of msel. see table above. 10, 15 dc ? don?t connect. do not connect these pins to anything. 11 pdclk input power down clock. see table above. 13 msel input multiplier select pin. selects x16 when low, x24 when high. 14 refout output buffered reference output clock. controlled by refen. 16 x2 xo crystal connection. connect this pin to a crystal or leave unconnected for a clock.
ics548-05 t1/e1 clock multiplier clock synthesizer idt? t1/e1 clock multiplier 3 ics548-05 rev d 091511 application information series termination resistor clock output traces should use series termination. to series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 . decoupling capacitors as with any high performance mixed-signal ic, the ics548-05 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f should be connected between each vdd and gnd on pins 3 and 5, as close to the device as possible other vdd?s can be connected to pin 3. if refout is not used, then refen should be connected directly to ground. crystal load capacitors if a crystal is used, the de vice crystal connections should include pads for capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. to reduce possible noise pickup, use very short pcb traces (and no vias) been the crystal and device. the value of the load capacitors can be roughly determined by the formula c = 2(c l - 6) where c is the load capacitor connected to x1 and x2, and c l is the specified value of the load capacitance for the crystal. a typical crystal c l is 18pf, so c = 2(18 - 6) = 24pf. because these capacitors adjust the stray capacitance of the pcb, check the output frequency using your final layout to see if the value of c should be changed. for a clock input, leave x2 unconnected (floating). pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) the external crystal should be mounted next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi and obtain the best signal integrity, the 33 series termination resistor should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the ics548-05. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
ics548-05 t1/e1 clock multiplier clock synthesizer idt? t1/e1 clock multiplier 4 ics548-05 rev d 091511 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics548-05. these ratings, which are standard values for idt commercially rated par ts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v , ambient temperature 0 to +70 c item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.15 5.5 v parameter symbol conditions min. typ. max. units core operating voltage vdd 3.15 5.5 v input high voltage v ih x1/iclk pin, clock input only (vdd/2)+1 vdd/2 v input low voltage v il x1/iclk pin, clock input only vdd/2 (vdd/2)-1 v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh i oh = -4 ma 2.4 v output high voltage v oh cmos level, i oh = -4 ma vdd-0.4 v output low voltage v ol i ol = 4 ma 0.4 v supply current idd no load 5 ma power down supply current iddpd no load 1 a
ics548-05 t1/e1 clock multiplier clock synthesizer idt? t1/e1 clock multiplier 5 ics548-05 rev d 091511 ac electrical characteristics unless stated otherwise, vdd = 3.3 v , ambient temperature 0 to +70 c thermal characteristics short circuit current i os clk output 50 ma input capacitance msel, pdclk , refen 7pf frequency synthesis error both selections 0 ppm parameter symbol conditions min. typ. max. units input crystal or clock frequency 1.544 or 2.048 mhz output clock rise time t or 20% to 80% 1.5 ns output clock fall time t of 80% to 20% 1.5 ns output clock rise time t or 20% to 80%, ta = -40 to +85 c 1.7 ns output clock fall time t of 80% to 20%, ta = -40 to +85 c 1.7 ns output clock duty cycle t od at vdd/2 40 50 60 % start-up time vdd = 3.3 v to clk stable 10 ms maximum absolute jitter, short term 100 ps maximum absolute jitter, short term ta = -40 to +85 c150ps one sigma jitter 25 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w parameter symbol conditions min. typ. max. units
ics548-05 t1/e1 clock multiplier clock synthesizer idt? t1/e1 clock multiplier 6 ics548-05 rev d 091511 package outline and package dimensions (16-pin tssop) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information "lf" suffix to the part number are the pb-free configuration, rohs compliant. while the information presented herein has been checked for both accuracy and reliability, idt assumes no responsibility for either its use or for the infringement of any patents or other ri ghts of third parties, which would result from its use. no oth er circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications su ch as those requiring extended temperature range, high reliability , or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 548g-05 548g-05 tubes 16-pin tssop 0 to +70 c 548G-05T 548g-05 tape and reel 16-pin tssop 0 to +70 c 548g-05lf 548g05lf tubes 16-pin tssop 0 to +70 c 548g-05lft 548g05lf tape and reel 16-pin tssop 0 to +70 c 548g-05i 548g-05i tubes 16-pin tssop -40 to +85 c 548g-05it 548g-05i tape and reel 16-pin tssop -40 to +85 c 548g-05ilf 548g05il tubes 16-pin tssop -40 to +85 c 548g-05ilft 548g05il tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l symbol min max min max
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